A flash memory is typically configured by an array of multiplicity of memory cells aligned in the word line direction and the bit line direction. A memory cell is configured by a stacked gate structure in which a floating gate electrode, an interelectrode insulating film, and a control gate electrode are stacked in the listed sequence. As flash memory increases its storage capacity through densification, features within the memory cell are packed in tighter dimensions. Dimensions typically affected by the densification are widths of floating gate electrodes and element isolation trenches.
For instance, narrowing of the element isolation trenches makes formation of control gate electrode difficult since polysilicon film, typically employed as a control gate electrode material, needs to be filled in the narrowed gaps between the neighboring floating gate electrodes which are further narrowed by the presence of the interelectrode insulating film. One solution to this problem may be thinning the interelectrode insulating film.
Further, narrowing the width of the floating gate electrode subjects the floating gate electrode to relatively higher electric field through the interelectrode insulating film. This is because the width scaling often results in a floating gate electrode with a sharp tip which causes concentration and enhancement of electric field. The electric field concentration increases the risk of leakage current which negatively impacts the programming properties.